While integrated circuit technology evolves, 3D stacked chip technology is gaining increasing popularity to provide improved performance for many applications. In contrast to a system-on-a-chip (SOC) approach where functional blocks are formed on a single monolithic substrate, a 3D stacked chip structure may be formed consisting of a stack of dies with heterogeneous devices. As an example, a 3D stacked chip structure may comprise a RF circuit die, a die with a signal processing unit, a die with sensor function, and a die with a power management unit. These dies are bonded together in a stacking manner, thus realizing a system-in-a-package configuration with each functional unit optimized for desired performance and circuit density. These dies are typically joined together through bonding pads formed in their respective external passivation layers. The bonded result produces a 3D stacked chip structure having multiple dies of integrated circuitry.
Additionally, forming a 3D stacked chip structure has been shown to significantly reduce the communication path length between components on different integrated circuit dies, provided the vertical distances between the layers are much smaller than the individual die size. Thus, through stacking dies vertically, the overall system speed is typically increased. Such a system configuration may also save package size and consumes less power.
In order to enable the various circuits and devices in a 3D stacked chip structure, vertical electrical connections are generally formed to connect the various components integrated within the various stacked dies. Such electrical connections are typically realized by through-silicon vias (TSVs) that are fabricated passing completely through a die, thereby providing electrical connections between the devices formed in the different dies of the bonded chip stacking structure.
It is realized, however, that the 3D stacked chip structure may generate a significant amount of heat while such a system is in operation. As a result, the issue of heat dissipation in a 3D stacked chip structure should be raised and addressed, and solutions be sought in order to maintain the reliability and the desired performance of a stacked chip structure where high power consumption leads to a high operating temperature.